1. Field of the Invention
The present invention is a method and apparatus for controlling input data flow into an asynchronous serial data communication device with a buffered parallel interface of limited bandwidth.
2. Description of the Prior Art
A wide variety of asynchronous communication devices are conventionally connected to host computer systems. Generally, this connection has been made using an integrated chip device known as a UART, an acronym for Universal Asynchronous Receiver Transmitter. A UART connected to a host computer system permits the host computer to send or receive units of data or information, usually called characters. UARTs generally receive data one character at a time, with the character transmitted serially, one bit at a time. Most operate under the control of a program on the host processor to which they are connected. This program may poll the connected UARTs to determine whether they are ready to receive or transmit another character. The host processor may also take interrupts from UARTs, with each UART issuing an interrupt when it is ready to receive or transmit another character.
UARTs have evolved into three functional types: (1) unbuffered UARTs, (2) buffered UARTs, and (3) direct memory access (DMA) UARTs. Each of the UART types below represents a trade-off in expense, speed, need for host processor servicing and the risk of lost data when used in high speed communication. The latter risk is increasingly significant, because of the great increase in networking, data communications traffic and transmission speeds. Many host systems are now connected to many different high-speed communication devices, including other computers, so that the volume of incoming data transmission at peak times could easily overwhelm the host processor, causing data loss.
1. Unbuffered UARTS
This type of UART has a transmit holding register linked to a transmit shift register that is connected to the telecommunications line. The transmit shift register can take in data bit-by-bit from the communication line or it can transmit data bit-by-bit onto the communication line. To send a character, the host processor stores it in the transmit holding register. When the transmit shift register becomes empty, the internal UART logic moves the next character from the transmit holding register to the transmit shift register. The character is then shifted and transmitted a bit at a time until it is completely transmitted. In order to maintain full speed operation, by the time transmission of one character is complete the processor must have stored another character into the transmit holding register so that it will be ready to be moved to the shift register and transmitted. Thus, transmission speed suffers when the processor is not able to keep the transmit holding register filled.
When receiving a character, the UART shifts data a bit at a time into a receive shift register. When a complete character has been received, the internal UART logic moves the character to a receive holding register where the host processor can read it. If the processor has not read that character by the time the next input character is fully received into the shift register, then the next character overwrites the character in the receive holding register, causing data loss. To avoid this, the processor must arrange to read each character arriving in the receive holding register within one input character arrival time. Accordingly, processor speed and polling or interrupt servicing of the UART must be adequate. Specifically, this type of UART requires the processor to service the asynchronous line at the incoming character transmission rate. Most often there are 10 bits/character. Thus, if a transmission line runs at 9600 baud, the host must service the UART 960 times/second.
2. Buffered UARTs
These UARTS improve the above design by replacing the transmit or receive holding registers with a FIFO (First-in-First-out) buffer. Due to the cost of buffer storage, early, inexpensive UARTs often had buffer storage for only 2-3 bytes. Newer UARTs most often have buffers of 16-64 bytes. Buffered UARTs can significantly reduce the servicing demands on the processor running the servicing program. For example in a UART with 16 byte receive and transmit buffers, the processor in theory only needs to service the chip every 16 characters, greatly reducing processor overhead caused by execution of the UART servicing routines.
3. DMA UARTs
These UARTs improve both the above designs by providing on-chip DMA circuitry to transfer incoming and outgoing data directly to host processor memory without interaction from the processor. This type of UART provides extremely high performance with low processor overhead, but requires much more expensive hardware. The UART chip must be provided with full bus access circuitry, and the processor memory subsystem must allow DMA access. For this reason, such UART chips are generally much more expensive. Thus, while DMA UARTs may help solve the problem of lost incoming data, they are not cost effective in many applications.
When designing nearly all types of data communication systems, it is necessary to prevent a sender from sending an unlimited amount of data to a slow receiver, causing data loss. The method for doing this is called flow control. It is usually implemented so that when the receive buffers contain more than a specified amount of data, the receiver requests the sender to stop transmitting temporarily, until the receive buffers can be emptied. Such requests to the sender can be in-band or out-of-band signals. To request the sender to stop with an in-band signal, the receiver may send an XOFF character, and then inform the sender to resume by sending an XON character. Conversely the receiver may request the sender to stop by dropping the out-of-band signal CTS (Clear to send) when the buffer becomes full, and then raising the CTS again when some of the data has been drained from the buffer.
It would seem natural to eliminate the lost data problem in communication systems by using flow control to tell the sender to slow down when the receiver is unable to remove received data from the UART buffers quickly enough to prevent data loss. Unfortunately, this solution will seldom work in practice, unless the flow control mechanisms are built into the UART hardware. In most cases, the receiving system recognizes that it has fallen behind in removing data from the UART only when the UART signals that data has already been lost. At that point it is too late to do anything about it. It is also common for the sender to delay in stopping data after receipt of the flow control signal, further complicating the problem. The stopping period is referred to as the "skid" interval, and for common computer systems is often 16 bytes.
A group of UARTs is often serviced by one processor. This requires that the processor have a polling and servicing method that permits it to service all UARTs, which at any given time may have widely varying transmit and receive traffic. In this arrangement, it is common to design a system so that adequate processing and memory bandwidth is provided to handle an average communication load, but not necessarily the worst case bi-directional load on all ports simultaneously. Such a system provides excellent performance at minimum cost, but may lose data under unusually high load conditions.
In the prior art, it has been proposed to optimize the operation of a group of UARTs by introducing certain features into the software that controls the UARTs. In U.S. Pat. No. 5,210,830, operation of a multiport communications processor is optimized by dynamically configuring the UART polling loop with at least one jump table. In U.S. Pat. No. 5,247,617, transmit polling of buffered UARTs is improved by predicting, for each polling interval, the minimum number of characters needed to keep the transmitter from going idle before the next polling interval and placing exactly that many characters in the transmittal FIFO buffer.
In the prior art, it has also been proposed to exercise flow control for incoming data based on the level of characters in the receive buffer of a UART. The UART is designed to assert flow control when the UART receive buffer contains more than a specified number of characters (the high water mark) and then release flow control when the number of characters drops below a different, smaller number (the low water mark). However, if the levels selected do not fit the application well, then receive buffer overflow and data loss can still occur.